18.3 MCP23017– Port Extender

• 16-bit remote bidirectional I/O port

  • I/O pins default to input

• High-speed I2C™ interface (MCP23017)

100 kHz

400 kHz

1.7 MHz

• High-speed SPI interface (MCP23S17)

  • 10 MHz (max.)

Three hardware address pins to allow up to eight devices on the bus

Configurable interrupt output pins

  • Configurable as active-high, active-low or open-drain

INTA and INTB can be configured to operate independently or together

Configurable interrupt source

  • Interrupt-on-change from configured register defaults or pin changes

Polarity Inversion register to configure the polarity of the input port data

External Reset input

Low standby current: 1 µA (max.)

Operating voltage:

Figure 63: MCP23017

1.8V to 5.5V @ -40°C to +85°C

2.7V to 5.5V @ -40°C to +85°C

4.5V to 5.5V @ -40°C to +125°C

Packages

28-pin PDIP (300 mil)

28-pin SOIC (300 mil)

28-pin SSOP

28-pin QFN

Functional Block Diagram

Device Overview

The MCP23017/MCP23S17 (MCP23X17) device family provides 16-bit, general purpose parallel I/O expansion for I2C bus or SPI applications. The two devices differ only in the serial interface.

  • MCP23017 – I2C interface
  • MCP23S17 – SPI interface

The MCP23X17 consists of multiple 8-bit configuration registers for input, output and polarity selection. The system master can enable the I/Os as either inputs or outputs by writing the I/O configuration bits (IODIRA/B). The data for each input or output is kept in the corresponding input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master.

The 16-bit I/O port functionally consists of two 8-bit ports (PORTA and PORTB). The MCP23X17 can be configured to operate in the 8-bit or 16-bit modes via

IOCON.BANK.

There are two interrupt pins, INTA and INTB, that can be associated with their respective ports, or can be logically OR’ed together so that both pins will activate if either port causes an interrupt.

The interrupt output can be configured to activate under two conditions (mutually exclusive):

  1. When any input state differs from its corresponding Input Port register state. This is used to indicate to the system master that an input state has changed.
  2. When an input state differs from a preconfigured register value (DEFVAL register).

The Interrupt Capture register captures port values at the time of the interrupt, thereby saving the condition that caused the interrupt.

The Power-on Reset (POR) sets the registers to their default values and initializes the device state machine.

The hardware address pins are used to determine the device address.

Pinout Description

Pin PDIP/ QFN Pin Type Function
GPB0 1 25 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB1 2 26 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB2 3 27 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB3 4 28 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB4 5 1 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB5 6 2 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB6 7 3 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPB7 8 4 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
VDD 9 5 P Power
VSS 10 6 P Ground
NC/CS 11 7 I NC (MCP23017), Chip Select (MCP23S17)
SCL/SCK 12 8 I Serial clock input
SDA/SI 13 9 I/O Serial data I/O (MCP23017), Serial data input (MCP23S17)
NC/SO 14 10 O NC (MCP23017), Serial data out (MCP23S17)
A0 15 11 I Hardware address pin. Must be externally biased.
A1 16 12 I Hardware address pin. Must be externally biased.
A2 17 13 I Hardware address pin. Must be externally biased.
RESET 18 14 I Hardware reset. Must be externally biased.
INTB 19 15 O Interrupt output for PORTB. Can be configured as active-high, active-low or open-drain.
INTA 20 16 O Interrupt output for PORTA. Can be configured as active-high, active-low or open-drain.
GPA0 21 17 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA1 22 18 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA2 23 19 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA3 24 20 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA4 25 21 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA5 26 22 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA6 27 23 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.
GPA7 28 24 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor.

for data changes or for continually writing to the output latches.

A special mode (Byte mode with IOCON.BANK = 0) causes the address pointer to toggle between associated A/B register pairs. For example, if the BANK bit is cleared

I2c Interface

I2C Write Operation

The I2C write operation includes the control byte and register address sequence, as shown in the bottom of Figure 1-1. This sequence is followed by eight bits of data from the master and an Acknowledge (ACK) from the MCP23017. The operation is ended with a Stop (P) or Restart (SR) condition being generated by the master.

Data is written to the MCP23017 after every byte transfer. If a Stop or Restart condition is generated during a data transfer, the data will not be written to the

MCP23017.

Both “byte writes” and “sequential writes” are supported by the MCP23017. If Sequential mode is enabled (IOCON, SEQOP = 0) (default), the MCP23017 increments its address counter after each ACK during the data transfer.

I2C Read Operation

I2C Read operations include the control byte sequence, as shown in the bottom of Figure 1-1. This sequence is followed by another control byte (including the Start condition and ACK) with the R/W bit set (R/W = 1). The MCP23017 then transmits the data contained in the addressed register. The sequence is ended with the master generating a Stop or Restart condition.

I2C Sequential Write/Read

For sequential operations (Write or Read), instead of transmitting a Stop or Restart condition after the data transfer, the master clocks the next byte pointed to by the address pointer (see Section 1.3.1 “Byte Mode and Sequential Mode” for details regarding sequential operation control).

The sequence ends with the master sending a Stop or Restart condition.

The MCP23017 Address Pointer will roll over to address zero after reaching the last register address.

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